Publications

An information processing device receives a request signal, read out a user class or a storage region class the request signal requests, and generates an object corresponding to the read-out class, wherein each user class is a class relating to users and each storage region class is a class relating to storage regions utilized by the users, based on the generated object and the request signal. The information processing device executes a method corresponding to the object, and thereby acquire data corresponding to the request signal. The information processing device outputs the acquired data.

The control device, which operates due to a processor executing an object-oriented program, backs-up, to a storing section, respective first combinations of elements of a first object in which class structure relating to an application program is defined, and respective second combinations of elements of a second object in which class structure relating to a storage region used by an application program is defined. In a case in which generation of an object is necessary when the program is started, for the first object, the control device reads-out the respective first combinations from the storing section and generates the fist object, and, for the second object, the control device reads-out the respective second combinations from the storing section and generates the second object.

A navigation device includes a processor. The processor collects captured images that have been captured by an imaging device mounted at a vehicle, sets a destination, and determines a route to the destination based on the captured images that have been collected.

A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. In this paper, we propose the following to improve the footprint and the scalability of systolic arrays (1) column multithreading for reducing the number of physical units and maintaining the performance even for back-to-back floating-point accumulations; (2) a cascaded peer-to-peer AXI bus for a scalable multichip structure and an intra-chip parallel local memory bus for low latency; (3) multilevel loop control in any unit for reducing the startup overhead and adaptive operation shifting for efficient reuse of local memories. We designed a systolic array with a single column × 64 row configuration with Verilog HDL, evaluated the frequency and the performance on an FPGA attached to a ZYNQ system as an AXI slave device, and evaluated the area with a TSMC 28nm library and memory generator and identified the following (1) the execution speed of a matrix multiplication/a convolution operation/a light-field depth extraction, whose size larger than the capacity of the local memory, is 6.3× / 9.2× / 6.6× compared with a similar systolic array (EMAX); (2) the estimated speed with a 4-chip configuration is 19.6× / 16.0× / 8.5×; (3) the size of a single-chip is 8.4 mm2 (0.31× of EMAX) and the basic performance per area is 2.4×.

Outstanding Originality Award
CGRA is a two-dimensional array of processing units, like an adders and multipliers connection by a mesh-like interconnect. The computation has to be laid out in space and time, and the data explicitly routed through the interconnection in the application code.